1. Field of the Invention
The present invention relates to a branched command/address bus architecture for registered memory units between a memory register and a plurality of memory units of a memory module.
2. Description of Prior Art
In memory architectures with registered memory units and memory chips, respectively, a suitable command/address bus architecture must be provided between the memory register and the memory units. In such an architecture a main bus connected to the memory register branches into a plurality of memory unit buses, wherein each memory unit bus is connected to an associated memory unit. Depending on the memory unit number used and the arrangement of the same, respectively, an asymmetric network may result by realizing such a bus branching, which is not symmetrical and balanced, respectively, due to the unbalanced distribution of the loads connected to the respective sub-branches of the network. Such an asymmetry results if a first sub-bus which is connected to a main bus connected to the memory register branches into a plurality of memory unit buses, while a second sub-bus also connected to the main bus branches into a second number of memory unit buses which is less than the first number.
In order to balance an asymmetry of the above-described type, an extra trace length has been used for the sub-bus which branches into the smaller number of memory unit buses in order to achieve a greater delay for this less loaded sub-bus or branch, respectively. With this approach, however, an unbalance and an asymmetry remain, respectively, which may cause an overshoot (ringing) and a slope reversal. These effects of a “ringing” or of oscillations caused due to the asymmetry degrade the signal quality considerably.